YOUR FUTURE RESPONSIBILITIES
- Coordination of infrastructure ramp up for FOWLP line at Silicon Austria labs
- Development and optimization of FOWLP processes for both chip-first and chip-last approaches, including die placement, wafer-level molding, processing of RDL & TMV.
- Designing fan-out package layouts, considering electrical performance, thermal dissipation, and reliability.
- Concept development, DOE planning, and characterization in an interdisciplinary team
- Development of FOWLP SIP for Power Electronics, MEMS and RF devices
- Contributing to different industrial projects
- Data analysis
- Technical reporting and scientific dissemination
- Project management
YOUR PROFILE
M.Sc. + 7 years of relevant working experience (or higher) in Physics, microsystems fabrication, power electronics and electronics engineering or relevant industrial experienceIn-depth knowledge and hands-on experience with FOWLP processes, materials, and equipment.Familiarity with packaging design tools, such as Cadence or Mentor Graphics for layout and design rule checksCleanroom and microfabrication experienceProject management experience as well as research funding proposalsFluent oral and written communication skills in English, knowledge of German is a plusIMPORTANT FACTS ABOUT SAL
Start of your employment as soon as possible.State-of-the-art laboratory facilities and instruments.Internal and external training opportunities for further technical and personal development.Flexible working time and possibilities for Home Office .4 / day food allowance in restaurants / € 2 / day in supermarkets.Family & kids friendly.Free coffee / milk / tea.