Project manager silicon design fmd Jobs in Vienna

We are Siemens

Siemens EDA  is a global technology leader in electronicdesign automation software. Our software tools enable companies around theworld to develop new and highly innovative electronic products faster and morecost-effectively. Our customers use our tools to push the boundaries oftechnology and physics in order to deliver better products in the increasinglycomplex world of chip, board and system design.

Tessent EmbeddedAnalytics, part of Siemens EDA, is a pioneering developer of analytics andmonitoring technology at the heart of the systems-on-chip (SoCs) that powertoday’s electronic products. Our embedded analytics technology allows productdesigners to add sophisticated cybersecurity, functional safety and performancetuning features; and it helps resolve critical issues such as increasing systemcomplexity and ever- decreasing time-to-market. We are proud of our technologyand selling globally to many of the most respected and most exciting technologycompanies in the world.

What we’re lookingFor

Do you have expertisein silicon IP and digital design using RTL languages? re you a VerificationEngineer with experience of verifying silicon IP? We are looking for ahighly capable and dedicated Digital Design or Verification Engineers to join ourgrowing team here at Ifyou can you see yourself learning, growing, and succeeding in this excitingposition and would relish the opportunity help shape the development of TessentEA’s ground-breaking silicon IP then we would love to meet you!

What you’ll be doing

• Verifying our IP from devising a verification plan through to coverage closure
• Collaborate with design and architecture teams to understand design specifications and develop verification strategies.
• Accessing advanced tools and opportunities to influence the features of Mentor verification tools
• Develop and execute detailed verification plans for ASIC designs, ensuring comprehensive coverage of all design features and functionalities.
• Create and maintain reusable, scalable, and robust testbenches using industry-standard verification languages and methodologies (e.g., SystemVerilog, UVM).
• Identify, analyze, and debug design issues, working closely with design engineers to resolve them in a timely manner.
• Utilize and enhance automated verification tools and scripts to improve efficiency and coverage.
• Mentor and provide technical guidance to junior verification engineers, fostering a culture of continuous learning and improvement.
• Stay up-to-date with industry trends and advancements in verification methodologies and tools, integrating best practices into the verification process.

What you’ll bring

Nice if you have

Join our DigitalWorld

We are an equalopportunity employer and value diversity at our company. We do not discriminateon the basis of race, religion, colour, national origin, sex, gender, genderexpression, sexual orientation, age, marital status, veteran status, ordisability status.

We offer acomprehensive reward package which includes a competitive basic salary, bonusscheme, generous holiday allowance, pension, private healthcare and activelysupport working from home.

We will ensure thatindividuals with disabilities are provided reasonable accommodation toparticipate in the job application or interview process, to perform essentialjob functions, and to receive other benefits and privileges of employment.Please contact us to request accommodation.

Siemens Software. Transformthe everyday!

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