Digital Verification Engineer

Join the semify team and contribute to cutting-edge electronic products and digital design for ASICs and FPGAs . We're a young and growing company with exciting and innovative projects, and we're looking for a talented Junior Digital Design Engineer to join our versatile team located in Graz, Austria. This is an opportunity to learn and grow your skills while working with experienced senior engineers who are committed to helping you succeed.

Tasks

As a Junior Digital Design Engineer at semify, you will play a critical role in implementing and verifying digital designs, developing FPGA-based prototypes and directly interacting with our industry-leading customers to help them solve their problems. You'll be part of a dynamic and growing team that is dedicated to making

an impact.

Requirements

As an ideal candidate for the position you :

• Are familiar with HDL description languages (SystemVerilog preferred)
• Can implement basic synchronous digital designs for ASICs or FPGAs
• Can understand and write Python scripts
• Are used to working with version control systems (Git preferred)
• Enjoy working in a distributed team

But most importantly - we welcome individuals who are willing to learn and grow with us!

Benefits

We believe in the power of international talent and cooperation . With the European Chips Act set to have a significant impact on the industry, there is a growing need for skilled professionals. By joining semify, you can actively participate in shaping the bright future of the European semiconductor landscape.

What we offer :

Working Hours

At semify, we believe in providing a flexible work environment that enables our team members to balance their personal and professional commitments. As such, we also welcome applications for our current position from individuals pursuing a work-friendly master's degree. The position itself offers a flexible weekly working schedule ranging from 20 to 38.5 hours, allowing you to tailor your work hours to your individual needs. Join our team and benefit from our commitment to worklife balance.

Payment

This position is endowed with a monthly salary of € 2.711 based on 38.5 hours (over payment possible). The collective agreement for ”Informationstechnologie“ is applied. Semify offers also a benefits package that includes meal vouchers and subsidies for public transportation.

Don't miss out on this unique opportunity to work on cutting-edge projects and to develop your skills as a Junior Digital Design Engineer. Apply now and become a part of the semify team!

Design Service for Mixed Signal ASICs :

Supporting the development process from concept to implementation. Providing digital design and verification service for mixed signal ASICs with a special focus on RISC-V based microcontroller systems for edge and IoT applications.

Evaluation Board Development :

Development of application specific evaluation boards. Evaluation boards with or without a microcontroller are developed depending on application needs. Supporting the development of FPGA based evaluation boards if specific digital control logic is required.

FPGA development :

Providing design service for FPGA based prototyping systems and applications. Special focus and experience with the development of RISC-V based microcontroller systems.